rtl-design-and-verification

Custom Altera FPGA designs by Olaoluwa Raji. This repository contains numerous projects that were successfully implemented on an Altera Cyclone IV FPGA using VHDL.

"Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"

A go-to repository for exploring, learning, and mastering RTL design and verification.

Implement a synthesizable 32-bit RISC-V RV32I processor with a 5-stage pipeline, hazard detection, and data forwarding for FPGA verification.

A modular and fully synthesizable 3-level (L1/L2/L3) cache memory subsystem implemented in SystemVerilog, featuring split L1 caches, a centralized L2, and a Last-Level L3 cache with coherence support.

Parameterized NxN systolic-array NPU for signed matrix multiplication, implemented in SystemVerilog RTL and verified using UVM, SVA, directed testing, formal verification, functional coverage, and multi-configuration regression.

RISC-V RV32IM Core

RV32I 5-Stage Pipelined CPU

AtlasRV32 — 32-bit RISC-V pipelined processor with hazard detection and data forwarding, synthesized on Artix-7 FPGA

Fully-streaming FPGA Top-of-Book engine with O(log₂N) pipelined arbiter achieving 223.4 MHz on Artix-7.

Digital Alarm Clock in Verilog HDL | FSM | ModelSim | Intel Quartus Prime | FPGA RTL Design

RTL Design and Verification of a Parameterized Synchronous FIFO in Verilog with directed, corner, and randomized test cases.

Parameterized 16-bit ALU designed in Verilog HDL with functional verification, synthesis, RTL schematic, and gate-level netlist.

RTL design and functional verification of a 32-bit ALU using Verilog HDL. Supports arithmetic, logical, and shift operations with corner-case handling such as divide-by-zero, underflow, and tri-state output enable. Simulated and verified using Xilinx ISE.

Dive into the world of SystemVerilog with hands-on projects that bring RTL design and verification to life! From blinking counters to smart assertions, this repo is my personal sandbox for mastering the language behind modern chip design. Whether you're a VLSI enthusiast, an aspiring verification engineer, or just curious about how hardware think.

UVM-based verification of an I2C master controller with RTL design, waveform analysis, and Vivado synthesis

8-bit ALU RTL design and verification in SystemVerilog — self-checking testbench, SVA assertions, functional coverage

Designed and verified an 8×8 synchronous FIFO in Verilog with full/empty flag logic using a self-checking testbench, reference model, and randomized test cases.

RTL implementation and class-based verification of a Direct-Mapped Cache Controller using SystemVerilog with a self-checking scoreboard, directed and constrained-random testing.