Synchronous FIFO Design & Functional Verification

Overview

Designed and verified an 8×8 synchronous FIFO in Verilog with full/empty flag generation, simultaneous read/write support, and overflow/underflow protection. A self-checking testbench verifies the design using a reference model, directed test cases, randomized transactions, and automatic PASS/FAIL reporting.

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Features

• 8×8 Synchronous FIFO
• Verilog RTL Design
• Full & Empty Flag Logic
• Simultaneous Read/Write Support
• Overflow & Underflow Handling
• Self-Checking Testbench
• Reference Model (Golden Model)
• Directed Test Cases
• Randomized Verification
• PASS/FAIL Reporting
• Transaction Statistics

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Verification Performed

• FIFO Reset Verification
• FIFO Fill Operation
• Full Flag Verification
• Overflow Testing
• FIFO Read Operation
• Empty Flag Verification
• Underflow Testing
• Random Read/Write Transactions
• Data Integrity Verification

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Project Structure

FIFO/
│── fifo_source.v      # FIFO RTL Design
│── fifo_tb.v          # Verification Testbench
│── README.md

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Tools Used

• Verilog HDL
• Xilinx ISE 14.7
• ISim Simulator

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Sample Output

==========================================
      FIFO VERIFICATION REPORT
==========================================
Transactions : 28
Writes       : 14
Reads        : 11
Overflow     : 1
Underflow    : 2
PASS         : 11
FAIL         : 0
==========================================

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Skills Demonstrated

• RTL Design
• Verilog HDL
• Functional Verification
• Testbench Development
• Reference Model
• Random Test Generation
• Digital System Design
• Simulation & Debugging

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Future Improvements

• Parameterized FIFO
• Asynchronous FIFO
• SystemVerilog Testbench
• Driver, Monitor & Scoreboard
• Mailbox-Based Verification
• Functional Coverage
• UVM Verification Environment

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Author

Shrawani Wagh

B.Tech Electronics & Telecommunication Engineering
Interested in VLSI Design, Functional Verification, Embedded Systems, and AI/ML