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Hajjy22/README.md

Hi there 👋

I am an Embedded Systems and ASIC/FPGA engineer. My interests sit where digital hardware design meets the firmware that runs on it. ✌️

I build RISC-V cores, CNN accelerators and the connected devices they end up in. INPT graduate, previously at Siemens EDA.

LinkedIn Email Upwork GitHub


Working with

SystemVerilog, Verilog, VHDL, UVM, C, C++, Python Vivado, Quartus, STM32, ESP32, FreeRTOS, MQTT

Building

  • AtlasRV32, a 32-bit RISC-V core with a 5-stage pipeline on Artix-7
  • A CNN accelerator taken through the ASIC flow at 206 MHz
  • I2C master IP for Nios II, verified past 90% functional coverage

Stats

Open to full time roles and freelance RTL or embedded work.

Pinned Loading

  1. AtlasRV-32-bit-RISC-V-Pipelined-Processor AtlasRV-32-bit-RISC-V-Pipelined-Processor Public

    AtlasRV32 — 32-bit RISC-V pipelined processor with hazard detection and data forwarding, synthesized on Artix-7 FPGA

    SystemVerilog 1