v1.19.0

Added

• stream_to_mem: Allows to use memories with flow control (req/gnt) for requests but
  without flow control for output data to be used in streams.
• isochronous_spill_register: Isochronous clock domain crossing cutting all paths.
• rr_arb_tree_tb: Systemverilog testbench for rr_arb_tree, which checks for fair throughput.
• cf_math_pkg::idx_width: Constant function for defining the binary representation width
  of an index signal.

Changed

• addr_decode: Use cf_math_pkg::idx_width for computing the index width, inline documentation.
• lzc: Use cf_math_pkg::idx_width for computing the index width, inline documentation.
• Bender: Change levels of modules affected by depending on cf_math_pkg::idx_width().
• stream_xbar: Fully connected stream bassed interconnect with variable number of inputs and outputs.
• stream_xbar: Fully connected stream-bassed interconnect with a variable number of inputs and outputs.

Fixed

• Improve tool compatibility.
• rr_arb_tree: Properly degenerate rr_i and idx_o signals.
• rr_arb_tree: Add parameter FairArb to distribute throughput of input requests evenly when
  not all inputs have requests active.
• stream_demux: Properly degenerate inp_sel_i signal.

v1.18.0

Added

• stream_fork_dynamic: Wrapper around stream_fork for partial forking.
• stream_join: Join multiple Ready/Valid handshakes to one common handshake.
• SECDED (Single Error Correction, Double Error Detection) encoder and decoder
• SECDED Verilator-based testbench
• Travis build for SECDED module

v1.17.0

Added

• stream_fifo: Ready/Valid handshake wrapper around fifo_v3

v1.16.4

Fixed

id_queue: Fix generation of head_tail_q registers

There are HT_CAPACITY registers behind the head_tail_q signal, and
the value of HT_CAPACITY need not necessarily be the same as
CAPACITY.

1.16.0 - 2020-01-13

• Handle degenerated onehot_to_bin with ONEHOT_WIDTH == 1
• Handle degenerated id_queue with CAPACITY == 1 or HT_CAPACITY == 1
• Fix cdc_fifo_gray to be a safe clock domain crossing (CDC)

1.15.0 - 2019-12-09

1.15.0 - 2019-12-09

Added

• Added address map decoder module

Fixed

• Handle degenerated lzc with WIDTH == 1

1.14.0 - 2019-10-08

1.14.0 - 2019-10-08

Added

• Added spubstitution-permutation hash function module
• Added couning-bloom-filter module
• spill_register: Added Bypass parameter
• counter: Added sticky overflow
• Added counter with variable delta
• Added counter that tracks its maximum value

Changed

• Added formal testbench for fifo and fall_through_regsiter

v1.13.1

Changed

• Fix path in src_files.yml for stream_arbiter and stream_arbiter_flushable

v1.13.0

Added

• Added exponential backoff window module
• Added parametric Galois LFSR module with optional whitening feature
• Added cf_math_pkg: Constant Function implementations of mathematical functions for HDL elaboration

Changed

• Parametric payload data type for rr_arb_tree

Deprecated

• The following arbiter implementations are deprecated and superseded by rr_arb_tree:
• Priority arbiter prioarbiter
• Round-robin arbiter rrarbiter

v1.11.0

Changes since 1.10

1.11.0 - 2019-03-20

Added

• Add stream fork
• Add fall-through register
• Add stream filter
• Add ID queue

Changed

• sync_wedge use existing synchronizer. This defines a single place where a tech-specific synchronizer can be defined.

Fixed

• Fix FIFO push and pop signals in stream_register to observe interface prerequisites.
• In fifo_v3, fix data output when pushing into empty fall-through FIFO. Previously, the data
  output of an empty fall-through FIFO with data at its input (and push_i=1) depended on
  pop_i: When pop_i=0, old, invalid data were visible at the output (even though empty_o=0,
  indicating that the data output is valid). Only when pop_i=1, the data from the input fell
  through. One consequence of this bug was that data_o of the fall_through_register could change
  while valid_o=1, violating the basic stream specification.