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Pull requests: llvm/circt

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Pull requests list

[Arc] Add $timeformat rendering to the SV runtime
#10645 opened Jun 12, 2026 by AmurG Contributor Loading…
1
[Arc] Add integer formatting to the SV runtime
#10644 opened Jun 12, 2026 by AmurG Contributor Loading…
1
[Arc] Add string comparison and slicing to the SV runtime
#10643 opened Jun 12, 2026 by AmurG Contributor Loading…
1
[Arc] Add a SystemVerilog execution runtime for the arcilator JIT
#10642 opened Jun 12, 2026 by AmurG Contributor Loading…
1
[Moore] Handle delayed assignments in concat-ref lowering
#10641 opened Jun 12, 2026 by AmurG Contributor Loading…
[Arc] Count operations across all blocks in SplitFuncs
#10640 opened Jun 12, 2026 by AmurG Contributor Loading…
1
[ImportVerilog] Thread $stacktrace caller context
#10639 opened Jun 12, 2026 by AmurG Contributor Loading…
1
[CombFolds] Restrict extract(concat(...)) canonicalization
#10638 opened Jun 12, 2026 by uenoku Member Loading…
1
1
[DRAFT][SimToSV] Lower sim.global_signal to SV
#10636 opened Jun 11, 2026 by nanjo712 Contributor • Draft
1
[slang] Update dependency to latest version.
#10635 opened Jun 11, 2026 by ingomueller-net Contributor Loading…
3
[slang] Update dependency to version 11.0.
#10634 opened Jun 11, 2026 by ingomueller-net Contributor Loading…
6
[ImportVerilog] Ignore let declarations
#10632 opened Jun 11, 2026 by AmurG Contributor Loading…
3
[MooreToCore] Observe class-backed event waits
#10630 opened Jun 11, 2026 by AmurG Contributor Loading…
3
[ImportVerilog] Hoist fork block declarations
#10629 opened Jun 11, 2026 by AmurG Contributor Loading…
5
[LLHD] Promote more process locals through mem2reg
#10628 opened Jun 11, 2026 by AmurG Contributor Loading…
7
[LLHD] Add conservative transform guards
#10624 opened Jun 11, 2026 by AmurG Contributor Loading…
4
Warn when FIRRTL needs and implicit truncation
#10621 opened Jun 10, 2026 by darthscsi Contributor • Draft
[Sim] Add sim.global_signal as named expression
#10616 opened Jun 10, 2026 by nanjo712 Contributor Loading…
22
[ImportVerilog][Moore][Sim] Add $timeformat system task support
#10614 opened Jun 10, 2026 by VecoMr Contributor Loading…
5
[ImportVerilog] Make making source locations proximate optional
#10613 opened Jun 10, 2026 by ingomueller-net Contributor Loading…
3
Optimize ConcatOp::canonicalize() processing of very large numbers of concat arguments
#10611 opened Jun 9, 2026 by rocallahan Contributor Loading…
16
[ImportVerilog][Moore] Add $fscanf/$sscanf and scan format support ImportVerilog Moore
#10605 opened Jun 9, 2026 by VecoMr Contributor Loading…
2
[VerifToSMT] Keep debug names in BMC
#10604 opened Jun 9, 2026 by 5iri Contributor Loading…
3
[ImportVerilog] Add option for absolute paths in source locations
#10599 opened Jun 8, 2026 by ingomueller-net Contributor Loading…
8
[ImportVerilog] Introduce enum builtin methods
#10595 opened Jun 5, 2026 by sunhailong2001 Contributor Loading…
5
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