[ImportVerilog] Thread $stacktrace caller context#10639
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Lower the `$stacktrace` system task by threading a hidden caller-location string argument into every subroutine that can reach a `$stacktrace` call, directly or transitively. The task prints a stack trace assembled from the subroutines currently being lowered plus the threaded caller frames.
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@fabianschuiki — this is a small, self-contained ImportVerilog change (CI green) with no reviewer assigned yet. Could you take a look, or point me to the right reviewer, when you have a cycle? Thanks. |
fabianschuiki
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There's quite a bit of code here to plumb stacktrace formatting through procedure lowering. Having this mixture of a stacktraceCallerStack, currentSubroutineStack, and a stacktraceCallerArgState feels extremely brittle and hard to maintain. How about we isolate the stacktrace threading logic into a separate Moore dialect pass, for example MaterializeStackTraces? We could have ImportVerilog emit a moore.builtin.stacktrace op, and then use MLIR's call graph infrastructure and DFS traversal (or a custom worklist) to figure out which subgraphs of the call graph need the parent's stack frame information. A second step of the pass could then thread the parent's stack context down into the caller. That would also make the stack trace accurately reflect what we end up having in the IR. WDYT?
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Full disclosure: AI generated text, via a human in CLI. @fabianschuiki — small, self-contained ImportVerilog $stacktrace fix, CI green and no dependencies. A review whenever you have spare bandwidth would be appreciated — no rush, and definitely lower priority than the sim-runtime work on #10642. |
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Closing (same reset as #10697), and answering the design question I left hanging: you were right, the |
Lower the
$stacktracesystem task by threading a hidden caller-location argument through to the called subroutine, so the stack trace reflects the SV call site. The caller context is recovered during import and passed as a synthesized argument.Part of a series upstreaming SystemVerilog/UVM simulation support validated against the sv-tests suite.
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