A library for accelerating Transformer models on NVIDIA GPUs, including using 8-bit and 4-bit floating point (FP8 and FP4) precision on Hopper, Ada and Blackwell GPUs, to provide better performance with lower memory utilization in both training and inference.

SOTA low-bit LLM quantization (INT8/FP8/MXFP8/INT4/MXFP4/NVFP4) & sparsity; leading model compression techniques on PyTorch, TensorFlow, and ONNX Runtime

Model compression toolkit engineered for enhanced usability, comprehensiveness, and efficiency.

An innovative library for efficient LLM inference via low-bit quantization

From-scratch C++/CUDA inference engine for the NVIDIA RTX 5090 (sm_120a) — the best single-GPU backend for agentic AI: tool calling, long-context loops, reasoning and concurrent sub-agents on top of the fastest single-stream decode on the 5090 (beats llama.cpp, at-or-ahead of vLLM on NVFP4). 100% written by Claude Code.

An stress and benchmark utility for NVIDIA GPUs. Measures performance across various precisions (FP64, FP32, TF32, FP16, INT8) and monitors real-time vitals like power, temperature, and clock speeds.

Narrow precision floating point types

Optimized vLLM setup for Gemma 4 31B NVFP4 with MTP on dual RTX PRO 6000 Blackwell using vllm and docker: native FP4 Tensor Cores, Multi-Token Prediction (96.5% acceptance rate), and prefix caching. Includes benchmark results and replication scripts.

LoRA fine-tune and serve NVFP4 models on one DGX Spark (GB10, 128 GB UMA): text backbones via generic-family onboarding, plus VLMs (vision tower, or LLM+tower jointly via --train-target both) validated end-to-end on Pixtral and Nemotron-Omni. Fused Triton dequant; runtime-LoRA and merge serving.

Python implementations for multi-precision quantization in computer vision and sensor fusion workloads, targeting the XR-NPE Mixed-Precision SIMD Neural Processing Engine. The code includes visual inertial odometry (VIO), object classification, and eye gaze extraction code in FP4, FP8, Posit4, Posit8, and BF16 formats.

The only deployed sparse FP4 GEMM on SM120: beats CUTLASS 80b on every shape, wins end-to-end request latency in 81 of 112 serving regimes vs dense NVFP4.

Three ComfyUI nodes that show the real runtime precision of MODEL, CLIP, and VAE objects.

Precision-spectrum GEMM roofline on NVIDIA Blackwell (sm_120), measured in CUDA — FP32 down to FP4, with FP4 (nvfp4) ~20x FP32 via cuBLASLt, anchored to the computed peak.

FP4 E2M1 Arithmetic Unit — Full RTL-to-GDSII tapeout on SKY130A PDK using OpenLane | 200 MHz timing closure | DRC/LVS clean | AI inference acceleration

Unlimited-OCR 的 OpenVINO 本地适配：显式 KV、R-SWA cache、12 层 sparse MoE decode、FP4/INT8 mixed experts

Kernel forge for the-den. Not just kernels. Kennels. Where the Hydra lives. Raw PTX tensor core path for Blackwell SM120. OMMA.SF.16864 cubins, SASS verification, fragment mapping. NVFP4-native.

Block-scaled FP8 / FP4 / INT4 tensor primitive with Triton scaled-matmul at FP32 parity on H100. NumPy / PyTorch / MLX / JAX backends.