Skip to content

Commit fc91ba9

Browse files
committed
added a1 and d1
1 parent 1a70dd6 commit fc91ba9

File tree

5 files changed

+116
-0
lines changed

5 files changed

+116
-0
lines changed

frontpanel/a1.go

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,42 @@
1+
package frontpanel
2+
3+
import "image"
4+
5+
func a1PortRectangles(layout portLayout) []image.Rectangle {
6+
padX := 2
7+
padY := 2
8+
9+
rectFor := func(x int, y int) image.Rectangle {
10+
return image.Rect(x+padX, y+padY, x+layout.width-padX, y+layout.height-padY)
11+
}
12+
13+
n := len(layout.topRowX)
14+
if len(layout.botRowX) < n {
15+
n = len(layout.botRowX)
16+
}
17+
18+
// A1 numbering: top then bottom at each column, left to right.
19+
rects := make([]image.Rectangle, 0, n*2+4)
20+
for i := 0; i < n; i++ {
21+
rects = append(rects,
22+
rectFor(layout.topRowX[i], layout.topY),
23+
rectFor(layout.botRowX[i], layout.botY),
24+
)
25+
}
26+
27+
rects = append(rects, a1RightSidePortRectangles()...)
28+
return rects
29+
}
30+
31+
func a1RightSidePortRectangles() []image.Rectangle {
32+
inset := func(r image.Rectangle, dx int, dy int) image.Rectangle {
33+
return image.Rect(r.Min.X+dx, r.Min.Y+dy, r.Max.X-dx, r.Max.Y-dy)
34+
}
35+
36+
// A1 ports 49-52 are SFP28 cages in a 2x2 grid (top-to-bottom, left-to-right).
37+
rect49 := inset(image.Rect(1670, 45, 1729, 84), 2, 2)
38+
rect50 := inset(image.Rect(1670, 113, 1729, 152), 2, 2)
39+
rect51 := inset(image.Rect(1731, 45, 1790, 84), 2, 2)
40+
rect52 := inset(image.Rect(1731, 113, 1790, 152), 2, 2)
41+
return []image.Rectangle{rect49, rect50, rect51, rect52}
42+
}

frontpanel/d1.go

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,42 @@
1+
package frontpanel
2+
3+
import "image"
4+
5+
func d1PortRectangles(layout portLayout) []image.Rectangle {
6+
padX := 2
7+
padY := 2
8+
9+
rectFor := func(x int, y int) image.Rectangle {
10+
return image.Rect(x+padX, y+padY, x+layout.width-padX, y+layout.height-padY)
11+
}
12+
13+
n := len(layout.topRowX)
14+
if len(layout.botRowX) < n {
15+
n = len(layout.botRowX)
16+
}
17+
18+
// D1 numbering: top then bottom at each column, left to right.
19+
rects := make([]image.Rectangle, 0, n*2+4)
20+
for i := 0; i < n; i++ {
21+
rects = append(rects,
22+
rectFor(layout.topRowX[i], layout.topY),
23+
rectFor(layout.botRowX[i], layout.botY),
24+
)
25+
}
26+
27+
rects = append(rects, d1RightSidePortRectangles()...)
28+
return rects
29+
}
30+
31+
func d1RightSidePortRectangles() []image.Rectangle {
32+
inset := func(r image.Rectangle, dx int, dy int) image.Rectangle {
33+
return image.Rect(r.Min.X+dx, r.Min.Y+dy, r.Max.X-dx, r.Max.Y-dy)
34+
}
35+
36+
// D1 ports 49-52 are four QSFP28 cages in a horizontal row at the bottom-right.
37+
rect49 := inset(image.Rect(1636, 130, 1695, 152), 2, 2)
38+
rect50 := inset(image.Rect(1697, 130, 1756, 152), 2, 2)
39+
rect51 := inset(image.Rect(1772, 130, 1831, 152), 2, 2)
40+
rect52 := inset(image.Rect(1833, 130, 1892, 152), 2, 2)
41+
return []image.Rectangle{rect49, rect50, rect51, rect52}
42+
}

frontpanel/frontpanel.go

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,12 @@ import (
2929
"golang.org/x/term"
3030
)
3131

32+
//go:embed images/7215-ixs-a1.webp
33+
var a1 []byte
34+
35+
//go:embed images/7220-ixr-d1.webp
36+
var d1 []byte
37+
3238
//go:embed images/7220-ixr-d2l.webp
3339
var d2l []byte
3440

@@ -44,6 +50,12 @@ type ChassisDef struct {
4450
}
4551

4652
var chassisImages = map[string]ChassisDef{
53+
"7215 IXS-A1": {
54+
Image: a1,
55+
},
56+
"7220 IXR-D1": {
57+
Image: d1,
58+
},
4759
"7220 IXR-D2L": {
4860
Image: d2l,
4961
},
@@ -88,6 +100,22 @@ type portLayout struct {
88100
}
89101

90102
var chassisPortLayouts = map[string]portLayout{
103+
"7215 IXS-A1": {
104+
topRowX: []int{178, 239, 299, 359, 419, 479, 540, 600, 682, 742, 802, 863, 922, 983, 1043, 1103, 1178, 1238, 1299, 1359, 1419, 1479, 1539, 1600},
105+
botRowX: []int{178, 239, 299, 359, 419, 479, 540, 600, 682, 742, 802, 863, 922, 983, 1043, 1103, 1178, 1238, 1299, 1359, 1419, 1479, 1539, 1600},
106+
topY: 42,
107+
botY: 106,
108+
width: 53,
109+
height: 48,
110+
},
111+
"7220 IXR-D1": {
112+
topRowX: []int{150, 208, 267, 326, 385, 445, 516, 576, 635, 694, 754, 813, 895, 955, 1015, 1073, 1133, 1192, 1264, 1323, 1383, 1441, 1501, 1560},
113+
botRowX: []int{150, 208, 267, 326, 385, 445, 516, 576, 635, 694, 754, 813, 895, 955, 1015, 1073, 1133, 1192, 1264, 1323, 1383, 1441, 1501, 1560},
114+
topY: 46,
115+
botY: 107,
116+
width: 53,
117+
height: 46,
118+
},
91119
"7220 IXR-D2L": {
92120
topRowX: []int{172, 233, 312, 374, 453, 514, 593, 655, 734, 795, 875, 936, 1015, 1077, 1156, 1217},
93121
botRowX: []int{172, 233, 312, 374, 453, 514, 593, 655, 734, 795, 875, 936, 1015, 1077, 1156, 1217},
@@ -506,6 +534,10 @@ func applyPortLabelOverlay(chassisType string, base image.Image) image.Image {
506534

507535
func portRectsForChassis(chassisType string, layout portLayout) []image.Rectangle {
508536
switch chassisType {
537+
case "7215 IXS-A1":
538+
return a1PortRectangles(layout)
539+
case "7220 IXR-D1":
540+
return d1PortRectangles(layout)
509541
case "7220 IXR-D2L":
510542
return d2lPortRectangles(layout)
511543
case "7220 IXR-D3L":

frontpanel/images/7215-ixs-a1.webp

52.4 KB
Loading

frontpanel/images/7220-ixr-d1.webp

46.5 KB
Loading

0 commit comments

Comments
 (0)