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IC Design Contest & Hardware Design Practice

本倉儲記錄了歷年教育部積體電路設計競賽 (IC Contest) 歷屆題目之自主實作,以及相關數位電路設計專案

競賽資訊

  • 層級: 研究所組 (Graduate Level)
  • 類別: Cell-Based Design (Group-B)
  • 製程參數: CBDK_IC_Contest_v2.5
  • 主要工具:
    • Simulator: vcs
    • Synthesis: Design Compiler
    • P&R: Cadence Innovus
    • Power Sign-off: Synopsys PrimePower (PTPX)
    • Physical Verification: Siemens Calibre

歷年實作成果 (Performance Dashboard)

: 針對不同題目的評分準則,下表 Timing 數據紀錄該設計之 Worst-case 以作為基準。

Year Topic Primary Metric Latency Power Area Status
2018 RF Indoor Localization Engine Time / Power 26.81 us 11.0 mW 363,746 um^2 Post Simulation
2019 IOT Data Filtering Time / Power 13.88 us 0.90 mW 11,415 um^2 Post Simulation
2021 Geofence Area 170.25 us 55,444 um^2 Gate Level Simulation
2025 Convex hull Time / Area 90.19 us 45,129 um^2 Gate Level Simulation
2026 Optical Refraction Time / Area 160.09 us 213,978 um^2 Gate Level Simulation

歷年實作詳細紀錄 (Detailed Verification Metrics)

點擊展開/摺疊歷年詳細測資數據

2018 | RF Indoor Localization Engine

  • Timing: Gate-level & Post-layout Cycle Time = 15.0 ns
  • Verification: APR Tool DRC/LVS = 0
  • Latency:
    Test Pattern Latency Power Note
    PAT1 26.81 us 10.9 mW
    PAT2 26.81 us 11.0 mW Worst Case
    PAT3 26.81 us 8.52 mW

2019 | IOT Data Filtering

  • Timing: Gate-level & Post-layout Cycle Time = 7.5 ns
  • Verification: APR Tool DRC/LVS = 0
  • Latency:
    Function Latency Power Note
    F1 11.55 us 0.72 mW
    F2 11.55 us 0.71 mW
    F3 13.88 us 0.90 mW Worst Case
    F4 11.54 us 0.74 mW
    F5 11.55 us 0.74 mW
    F6 11.54 us 0.69 mW
    F7 11.54 us 0.69 mW

2021 | Geofence

  • Timing: Gate-level Cycle Time = 50.0 ns

2025 | Convex hull

  • Timing: Gate-level Cycle Time = 8.0 ns
  • Latency:
    Test Pattern Latency Cycle Note
    PAT1 90.19 us 11273 Worst Case
    PAT2 79.79 us 9973
    PAT3 79.00 us 9874

2026 | Optical Refraction

  • Timing: Gate-level Cycle Time = 25.0 ns
  • Latency:
    RI Latency Note
    2~15 160.09 us

歷屆考題下載 (Resources)

如果你需要參考歷屆題目或初賽的完整資料,可以透過以下連結獲取:

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