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1. uart16550 uart16550 Public

   Forked from olofk/uart16550

   UART 16550 core

   Verilog 2 1

2. cr_sync cr_sync Public

   A simple parameratized flip-flop synchronizer to eliminate basic meta-stability issues.

   Verilog

3. cr_ram_r_w_2c cr_ram_r_w_2c Public

   A simple parameterized RAM for things like an asynchronous FIFO.

   Verilog

4. cr_gray2bin cr_gray2bin Public

   Gray Code to Binary Conversion

   Verilog

5. cr_bin2gray cr_bin2gray Public

   Binary to Gray Code Conversion

   Verilog 1

6. cr_fifoctl_s2_sf cr_fifoctl_s2_sf Public

   Synchronous Dual Clock FIFO Controller with Static Flags

   Verilog