RISC-V Core in VHDL for FPGA Implementation

This project implements a RISC-V processor core written in VHDL, designed for synthesis on an FPGA. It is developed as an academic project to explore computer architecture, digital design, and hardware synthesis workflows.

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Key Features

• Architecture: RISC-V RV32I
• HDL: VHDL
• Execution model: Single-cycle
• Main components:
  • Control Unit
  • ALU
  • ROM
  • RAM
  • Register banks
  • Imm. generator
  • Mem. Controller
  • GPIO
• FPGA compatibility: DE2-115-06

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Authors

• Rafael Budia Murcia, Paulina Chaufan Wax , Jorge Nisa Navarrete, Álvaro Roca Nacarino, Alejandro Saez Vega, Francesc Tudela Domenech
• Universitat Politècnica de València (UPV)
• 2024-2025