RISC-V: add reg_access and test its usages in C and Python

[moste00]

Your checklist for this pull request

• I've documented or updated the documentation of every API function and struct this PR changes.
• I've added tests that prove my fix is effective or that my feature works (if possible)

Detailed description

Capstone module callback reg_access is a convenience wrapper over the operands array that filters out the register operands (including those used as memory base address) from the rest of the operands and returns them sorted into read and written registers. It wasn't implemented for RISC-V, this PR implements it.

The following decisions were made for RISC-V's reg_access:

1- System registers (CSRs) are not registers

This follows existing Capstone convention, where almost every architecture that have system registers except x86 treats them as a seperate address space.

From a purely practical POV, the reg_access API returns registers as an array of integers, and the address space of normal registers intersects with that of system registers so there is nothing in the return value to distinguish them.

2- The PC is not an implicit register

Whenever an instruction reads PC (e.g. all call-ish instructions JAL[R]?) this is NOT counted as an implicit read of the PC.

The reason is that the PC is somewhat "second class" in RISC-V, it's an archiectural register but has no actual index and can never be directly written to by any instruction in any standard extension no matter the privliege.

Meanwhile, all instruction that read the PC have names that make it obvious they read the PC so adding that information to the implicit reads array would be redundant.

Again from a purely practical POV, the PC has no index defined by riscv.h, which makes sense as it's never referenced by any instruction.

Test plan

Added two unit tests to prove the callback can be run from the consumer side of the C and Python API of Capstone.

Closing issues

closes #2406 .

[moste00]

@Rot127 please review.