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- opt-vp Public
Virtual Prototype for identifying Application Specific Hardware Optimization candidates
- fdl-2026-mutationGeneration Public
Mutation generation script provided by our work "Exploring the Parameter Space for Constrained Random Verification of RISC-V CPUs"
- diviac Public
DIVIAC: Library of Input Data Aware Approximate Dividers with Partial Exact Minimization
- microrv32 Public
SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
- fv-lidac Public
FV-LIDAC: Formally Verified Library of Input Data Aware Approximate Arithmetic Circuits
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