New Features
- Added
axi4lite_VersionRegistermodule and necessary files:- Entity
axi4lite_GitVersionRegister - Package
mem_GitVersionRegister - Synthesis pre-TCL script
tools/git/preSynth_GitVersionRegister_Vivado.tcl - Entity
xil_DNAPort
- Entity
- Use
sync_Bitsfor CDC infifo_ic_got(code reruse and apply constraints automatically). - Added empty/fill-level output for
fifo_shift - Add chunk-enable feature for
comm_crc - Support for fraction of one for type
T_FRACTIONAL - Entity
list_expire - Entity
misc_Sequencer - Entity
misc_StrobeGenerator - Entity
misc_StrobeLimiter - Entity
misc_StrobeStretcher - Entity
mac_TX_Type_Prepender
Changes
- Check if Init value fits in
downcounter; changed Init value's type anatural. - Updated
my_configtemplate withGENERICas device example
Bug Fixes
bus_Arbiter: Throw failure when unimplemented lottery strategy is selected.- Added missing VHDL sources to
*.profiles for analyzing in simulators:- syntax check
- instantiation check
arith_scaler: Initialize arrays with'0'instead of'-'for better/easier simulationremote_terminal_control: Fix package name
Tests
- Run simulations additionally with GHDL mcode backend and NVC for better simulation coverage.
axi4lite_Register(see #20)- updated register definition
- added testcase for
- checking initial values on all registers
- simple read write
Clean-Up
- Remove all
*.files, since they are outdated and the compile order is now defined by the*.profiles usable with OSVVM-Scripting. - Remove old and unused VHDL files
sim/obsoleted by OSVVM- Xilinx ISE related files
Related Issues and Pull-Requests
Co-authored-by: Adrian Weiland <adrian.weiland@plc2.de>
Co-authored-by: Asif Iqbal <asif.iqbal@plc2.de>
Co-authored-by: Max Kraft-Kugler <max.kraft-kugler@plc2.de>
Co-authored-by: Jonas Schreiner <jonas.schreiner@plc2.de>
Co-authored-by: Patrick Lehmann <patrick.lehmann@plc2.de>
Co-authored-by: Patrick Lehmann <patrick.lehmann@tu-dresden.de>
Co-authored-by: Patrick Lehmann <paebbels@gmail.com>