This repository documents the end-to-end ASIC implementation of a 5-stage pipelined RISC processor, developed from RTL specifications down to the final physical layout (GDSII).
The project focuses on the Physical Design flow, achieving timing closure and optimizing for area/power using industry-standard EDA tools.
The physical implementation was split into the main functional blocks to optimize placement and routing.
| Datapath (DP) | Control Unit (CU) |
|---|---|
 |
 |
| Layout of the 5-stage Datapath | Layout of the Hardwired Control Unit |
The implementation followed a rigorous ASIC flow:
- RTL Design & Verification:
- Language: VHDL (Structural & Behavioral).
- Architecture: 5-Stage Pipeline (Fetch, Decode, Execute, Memory, Write-Back).
- Hazards: Handled via Forwarding Unit and Hazard Detection Unit (Stalling).
- Tool: Siemens QuestaSim.
- Logic Synthesis:
- Constraints: Optimized for Timing (WNS) and Area.
- Tool: Synopsys Design Compiler.
- Physical Design (P&R):
- Steps: Floorplanning, Power Ring/Stripe planning, Placement, Clock Tree Synthesis (CTS), Routing, DRC/LVS.
- Tool: Cadence Innovus.
Achieved full timing closure with positive slack under the target clock frequency.
| Metric | Value | Notes |
|---|---|---|
| Technology Node | 45nm (Nangate Open Cell Library) | |
| Frequency | 307.69 MHz | |
| Worst Negative Slack (WNS) | 0.917 ns | TIMING MET (Setup Clean) |
| Pipeline Stages | 5 | With Forwarding logic |
Detailed analysis of the datapath, control unit FSM, and physical constraints can be found in the technical report.
Note: Due to academic policy regarding the "Microelectronic Systems" course at Politecnico di Torino, the raw VHDL source code is not publicly available in this repository. This portfolio demonstrates the design methodology, flow proficiency, and final physical results.