Week 2 Lab: System Verilog

Fill out this readme as required by lab guidance

Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
cmake		cmake
dv		dv
rtl		rtl
.clang-format		.clang-format
.gitignore		.gitignore
CMakeLists.txt		CMakeLists.txt
ReadMe.md		ReadMe.md
vcpkg.json		vcpkg.json

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