Add Verilog RTL, simulators, and toolchain

[Elwimen]

Summary

• verilog/cpu.v — cycle-accurate single-cycle RTL: Harvard architecture, 8-bit datapath, 12-bit instructions, 13-instruction ISA, NAND-only ALU, $readmemh ROM init
• verilog/tb_cpu.v — automated testbench: injects help\n, captures TTY output, dumps VCD waveform; terminates in 12 000 cycles
• verilog/tb_interactive.v — interactive testbench via Icarus $fgetc; stdin → keyboard, stdout → TTY; exit with Ctrl-D
• verilog/Makefile — make sim / make isim / make wave / make clean
• cpu_sim.py — pure-Python cycle-accurate interactive simulator; raw terminal mode, backspace/Ctrl-D handling, --trace and --max-cycles flags
• extract_netlist.py — Logisim .circ → netlistsvg-compatible JSON; flood-fills 930 wire segments into 149 nets, decodes Splitter pin geometry, emits 11-cell Yosys-style JSON
• useless_OS_clean.hex — ROM image assembled from useless_OS_clean.asm
• README.md — full architecture docs, ISA table, memory map, I/O interface, tool usage, Verilog/Logisim correspondence table, expected simulation output
• .gitignore — exclude Verilog build artifacts and generated netlist files

Test plan

• cd verilog && make sim — automated testbench prints banner, responds to help, terminates cleanly at cycle 12003
• cd verilog && make isim — interactive shell accepts keyboard input, exit with Ctrl-D
• python3 cpu_sim.py — Python interactive shell, same behaviour
• python3 extract_netlist.py --summary — prints net table, writes cpu_netlist.json (11 cells, 149 nets)
• python3 assembler.py useless_OS_clean.asm — all 182 instructions match useless_OS.hex exactly