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We need to assert PAGE_SC_TRAP if either PTE_CW or PTE_CD are clear, as otherise we can end up caching a TLB entry without SC_TRAP for a PTE that's merely got PTE_CW without PTE_CD turned on. This is similar to the existing logic around PTE_D, though this commit adds some commentary clarifying the similarity. I assume the PTE_W/PTE_D test is phrased the way it is for optimization.
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We need to assert PAGE_SC_TRAP if either PTE_CW or PTE_CD are clear, as
otherise we can end up caching a TLB entry without SC_TRAP for a PTE
that's merely got PTE_CW without PTE_CD turned on.
This is similar to the existing logic around PTE_D, though this commit adds some
commentary clarifying the similarity. I assume the PTE_W/PTE_D test is phrased
the way it is for optimization.