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This repository was archived by the owner on Apr 27, 2023. It is now read-only.

Re-encode the multi-destination register instructions. #74

Description

@ben-marshall

The current encoding of the multi-precision and xc.mror instructions is very wasteful.

Current usage patterns are:

  • xc.madd.3 (a,b), c, d, a
  • xc.msub.3 (a,b), c, d, a
  • xc.mmul.3 (a,b), c, d, a
  • xc.macc.1 (a,b), a, b, c

Most of the time, a source and a destination register (or two) are the same.

Suggestions:

  • For xc.madd.3, xc.msub.3, xc.mmul.3, make what is now rs3 an implicit argument, which is always equal to the "low" destination register.
    • This frees up 32 code points per instruction.
  • For xc.macc.1, either:
    • Remove rs3, make rs1 a multi-register address and add rs2 to the catenation of rs1 registers, placing the result in rdm.
      • Frees up 32-code points.
    • Make rdm an implicit source register pair.
      • Frees up 256 code points.

For xc.mror:

  • make rs1 a multi-source register.
  • make rs2 the rotate ammount.

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implementationIssue relates to the hardware implementation of the iSEsoftwareIssue relates to the example software or modified binutils.specificationIssue relates to the XCrypto ISE specificationverificationIssue relates to the verification environment

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