[rv_dm,dv] Give rv_dm_if a passive mode

Doing this properly involves tidying up the clocking block a little
bit and defining a "mon_cb" version. Detailed changes:

  - The signals in the interface and the testbench are now listed in
    the same order as the ports of rv_dm. No functional change, but it
    should make the code slightly easier to read quickly.

  - The interface now has an is_active flag and the various signals
    that the testbench *might* drive (inputs to rv_dm) are now wires
    and driven with 'z in passive mode.

  - All the clocked signals are now in the clocking block. The commit
    removes scanmode and scan_rst_n from the block (because they are
    not synchronous to clk_i).

  - There is now a modport that groups together all the signals from
    the "point of view" of an active testbench.

  - The code in the rv_dm environment now consistently accesses
    signals through the modport.

  - For passive mode, the clocking block and modport are
    duplicated (as mon_cb and mon_mp) with all the signals as inputs.

Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>

Author: rswarbrick

hw/ip/rv_dm/dv/env/rv_dm_if.sv

@@ -6,24 +6,53 @@ interface rv_dm_if(input logic clk, input logic rst_n);
 
   import rv_dm_env_pkg::*;
 
-  // DUT inputs.
-  logic                 scan_rst_n;
-  logic [NUM_HARTS-1:0] unavailable;
+  // Most of the signals in the interface are designed to be connected to ports of rv_dm. If
+  // is_active is true, the signals that will be connected to its input ports are driven by cb. If
+  // is_active is false, they are driven with 'z here, which allows the interface to monitor a
+  // larger design that drives rv_dm itself.
+  //
+  // The flag is defined as a wire with a weak pull-up. This ensures that a testbench that doesn't
+  // customise is_active will see the interface be driven actively, but allows a testbench that
+  // *does* want to customise the signal to pull it low.
+  wire is_active;
+  assign (weak0, weak1) is_active = 1'b1;
 
-  // DUT outputs.
-  wire ndmreset_req;
-  wire dmactive;
-  wire [NUM_HARTS-1:0] debug_req;
+  // The signals connected to ports of rv_dm, other than the TL, alert, RACL and JTAG interfaces.
+  // These have the same name as the port, but without an _i or _o suffix.
+  wire logic                 scan_rst_n;
+  wire logic                 ndmreset_req;
+  wire logic                 dmactive;
+  wire [NUM_HARTS-1:0]       debug_req;
+  wire logic [NUM_HARTS-1:0] unavailable;
 
-  // Disable TLUL host SBA assertions when injecting intg errors on the response channel.
-  bit disable_tlul_assert_host_sba_resp_svas;
+  // "Internal" versions of the per-port signals above for rv_dm's input ports
+  logic                 scan_rst_n_internal;
+  logic [NUM_HARTS-1:0] unavailable_internal;
 
+  // Drive the wire signals for rv_dm's input ports if is_active is true
+  assign scan_rst_n  = is_active ? scan_rst_n_internal  : 'z;
+  assign unavailable = is_active ? unavailable_internal : 'z;
+
+  // A clocking block for driving the various _internal signals that are all synchronous to clk. If
+  // is_active is true, these can be used to drive input ports of rv_dm. The signals from output
+  // ports of rv_dm can also be sampled through this clocking block.
   clocking cb @(posedge clk);
-    output scan_rst_n;
-    output unavailable;
+    input  ndmreset_req;
+    input  dmactive;
+    input  debug_req;
+    output scan_rst_n = scan_rst_n_internal;
+    output unavailable = unavailable_internal;
+  endclocking
+
+  // A clocking block for a monitor
+  clocking mon_cb @(posedge clk);
     input ndmreset_req;
     input dmactive;
     input debug_req;
+    input unavailable;
   endclocking
 
+  // Disable TLUL host SBA assertions when injecting intg errors on the response channel.
+  bit disable_tlul_assert_host_sba_resp_svas;
+
 endinterface

hw/ip/rv_dm/dv/env/seq_lib/rv_dm_base_vseq.sv

@@ -246,21 +246,21 @@ class rv_dm_base_vseq extends cip_base_vseq #(
     uint delay;
     `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(delay, delay inside {[0:1000]};) // ns
     #(delay * 1ns);
-    cfg.rv_dm_vif.cb.scan_rst_n <= 1'b0;
+    cfg.rv_dm_vif.scan_rst_n_internal <= 1'b0;
     // Wait for core clock cycles.
     `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(delay, delay inside {[2:50]};) // cycles
     cfg.clk_rst_vif.wait_clks(delay);
     `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(delay, delay inside {[0:1000]};) // ns
-    cfg.rv_dm_vif.cb.scan_rst_n <= 1'b1;
+    cfg.rv_dm_vif.scan_rst_n_internal <= 1'b1;
   endtask
 
   virtual task apply_resets_concurrently(int reset_duration_ps = 0);
     int trst_n_duration_ps = cfg.m_jtag_agent_cfg.vif.get_tck_period_ps() * $urandom_range(5, 20);
-    cfg.rv_dm_vif.cb.scan_rst_n <= 1'b0;
+    cfg.rv_dm_vif.scan_rst_n_internal <= 1'b0;
     cfg.m_jtag_agent_cfg.vif.assert_test_reset();
     super.apply_resets_concurrently(dv_utils_pkg::max2(reset_duration_ps, trst_n_duration_ps));
     cfg.m_jtag_agent_cfg.vif.clear_test_reset();
-    cfg.rv_dm_vif.cb.scan_rst_n <= 1'b1;
+    cfg.rv_dm_vif.scan_rst_n_internal <= 1'b1;
   endtask
 
   virtual task dut_shutdown();
@@ -333,7 +333,7 @@ class rv_dm_base_vseq extends cip_base_vseq #(
 
     csr_wr(.ptr(jtag_dmi_ral.dmcontrol.haltreq), .value(1));
     if (!cfg.clk_rst_vif.rst_n) return;
-    `DV_CHECK_EQ(cfg.rv_dm_vif.cb.debug_req, 1)
+    `DV_CHECK_EQ(cfg.rv_dm_vif.mon_cb.debug_req, 1)
 
     // Wait a short time (up to 10 cycles, but stopping early if there's a reset)
     fork begin : isolation_fork

hw/ip/rv_dm/dv/env/seq_lib/rv_dm_mem_tl_access_halted_vseq.sv

@@ -11,7 +11,7 @@ class rv_dm_mem_tl_access_halted_vseq extends rv_dm_base_vseq;
     uvm_reg_data_t r_data;
     // Disable unavailable signal to make sure that hart should be in known state. if hart
     // is unavailable then it could not halted.
-    cfg.rv_dm_vif.unavailable <= 0;
+    cfg.rv_dm_vif.cb.unavailable <= 0;
 
     // Make sure that the ndmreset signal is not currently asserted. If it is asserted then DMI
     // operations work but the TLUL connection is blocked by u_tlul_lc_gate_rom, which is held in

hw/ip/rv_dm/dv/env/seq_lib/rv_dm_mem_tl_access_resuming_vseq.sv

@@ -44,7 +44,7 @@ class rv_dm_mem_tl_access_resuming_vseq extends rv_dm_base_vseq;
 
     // Disable unavailable signal to make sure that hart should be in known
     // state. If hart is unavailable then it could not halted.
-    cfg.rv_dm_vif.unavailable <= 0;
+    cfg.rv_dm_vif.cb.unavailable <= 0;
 
     // Request a halt as the debugger and then acknowledge it as the hart.
     request_halt();

hw/ip/rv_dm/dv/env/seq_lib/rv_dm_smoke_vseq.sv

@@ -59,9 +59,9 @@ class rv_dm_smoke_vseq extends rv_dm_base_vseq;
     cfg.rv_dm_vif.cb.unavailable <= data;
     csr_rd(.ptr(jtag_dmi_ral.dmstatus), .value(data));
     if (cfg.clk_rst_vif.rst_n) begin
-      `DV_CHECK_EQ(cfg.rv_dm_vif.unavailable,
+      `DV_CHECK_EQ(cfg.rv_dm_vif.mon_cb.unavailable,
                    get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data))
-      `DV_CHECK_EQ(cfg.rv_dm_vif.unavailable,
+      `DV_CHECK_EQ(cfg.rv_dm_vif.mon_cb.unavailable,
                    get_field_val(jtag_dmi_ral.dmstatus.allunavail, data))
     end
   endtask