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micprogmicprog
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Fix more slang warnings
1 parent 127ac64 commit 31b6cf2

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7 files changed

+46
-52
lines changed

7 files changed

+46
-52
lines changed

‎.github/workflows/ci.yml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -231,7 +231,7 @@ jobs:
231231
token: ${{ secrets.GITHUB_TOKEN }}
232232
slang-flags: >-
233233
-f hardware/spyglass/tmp/files --top ara_soc_wrap
234-
-Wextra -Wno-width-trunc -Wno-case-redundant-default
234+
-Wextra -Wno-width-trunc -Wno-case-redundant-default -Wno-case-enum -Wno-incomplete-return -Wno-dup-import
235235
--ignore-unknown-modules
236236
--suppress-warnings .bender/...,hardware/deps/...
237237

‎hardware/src/lane/lane_sequencer.sv‎

Lines changed: 28 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -744,18 +744,16 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
744744
// todo:
745745

746746
// Mask logical and integer comparisons
747-
operand_request[AluA] = '{
748-
id : pe_req.id,
749-
vs : pe_req.vs1,
750-
scale_vl: pe_req.scale_vl,
751-
vtype : pe_req.vtype,
752-
vstart : vfu_operation_d.vstart,
753-
hazard : pe_req.hazard_vs1 | pe_req.hazard_vd,
754-
target_fu : ALU_SLDU,
755-
conv : OpQueueConversionNone,
756-
cvt_resize: CVT_SAME,
757-
default : '0
758-
};
747+
operand_request[AluA] = '0;
748+
operand_request[AluA].id = pe_req.id;
749+
operand_request[AluA].vs = pe_req.vs1;
750+
operand_request[AluA].scale_vl = pe_req.scale_vl;
751+
operand_request[AluA].vtype = pe_req.vtype;
752+
operand_request[AluA].vstart = vfu_operation_d.vstart;
753+
operand_request[AluA].hazard = pe_req.hazard_vs1 | pe_req.hazard_vd;
754+
operand_request[AluA].target_fu = ALU_SLDU;
755+
operand_request[AluA].conv = OpQueueConversionNone;
756+
operand_request[AluA].cvt_resize = CVT_SAME;
759757
// Since this request goes outside of the lane, we might need to request an
760758
// extra operand regardless of whether it is valid in this lane or not.
761759

@@ -858,18 +856,16 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
858856

859857
// Vd register to provide correct mask undisturbed policy at bit-level
860858
// This is can be a mask or normal register
861-
operand_request[MaskB] = '{
862-
id : pe_req.id,
863-
vs : pe_req.vd,
864-
scale_vl: pe_req.scale_vl,
865-
vtype : pe_req.vtype,
866-
vstart : vfu_operation_d.vstart,
867-
hazard : pe_req.hazard_vd,
868-
target_fu : ALU_SLDU,
869-
conv : OpQueueConversionNone,
870-
cvt_resize: CVT_SAME,
871-
default : '0
872-
};
859+
operand_request[MaskB] = '0;
860+
operand_request[MaskB].id = pe_req.id;
861+
operand_request[MaskB].vs = pe_req.vd;
862+
operand_request[MaskB].scale_vl = pe_req.scale_vl;
863+
operand_request[MaskB].vtype = pe_req.vtype;
864+
operand_request[MaskB].vstart = vfu_operation_d.vstart;
865+
operand_request[MaskB].hazard = pe_req.hazard_vd;
866+
operand_request[MaskB].target_fu = ALU_SLDU;
867+
operand_request[MaskB].conv = OpQueueConversionNone;
868+
operand_request[MaskB].cvt_resize = CVT_SAME;
873869
// vl and eew depend on the real eew on which we are working on
874870
if (pe_req.op inside {VIOTA,VID}) begin
875871
// Non-mask layout
@@ -938,16 +934,14 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
938934
// VRGATHER and VCOMPRESS access the opreq with ad-hoc requests
939935
if (vrgat_state_q == REQUESTING) begin
940936
// Here, we are sure the MaskB operand_request is free
941-
operand_request[MaskB] = '{
942-
vs : masku_vrgat_req_q.vs,
943-
eew : masku_vrgat_req_q.eew,
944-
scale_vl : 1'b0,
945-
cvt_resize : pe_req.cvt_resize,
946-
vl : 1,
947-
vstart : masku_vrgat_req_q.idx,
948-
hazard : '0,
949-
default : '0
950-
};
937+
operand_request[MaskB] = '0;
938+
operand_request[MaskB].vs = masku_vrgat_req_q.vs;
939+
operand_request[MaskB].eew = masku_vrgat_req_q.eew;
940+
operand_request[MaskB].scale_vl = 1'b0;
941+
operand_request[MaskB].cvt_resize = pe_req.cvt_resize;
942+
operand_request[MaskB].vl = 1;
943+
operand_request[MaskB].vstart = masku_vrgat_req_q.idx;
944+
operand_request[MaskB].hazard = '0;
951945
operand_request_push[MaskB] = masku_vrgat_req_ready_d;
952946
end
953947
end: sequencer

‎hardware/src/lane/simd_alu.sv‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -309,19 +309,19 @@ module simd_alu import ara_pkg::*; import rvv_pkg::*; #(
309309
automatic logic [16:0] sub = opb.w16[b] - opa.w16[b];
310310
vxsat.w16[b] = (!opb.w16[b][15] & opa.w16[b][15] & sub[15]) |
311311
(opb.w16[b][15] & !opa.w16[b][15] & !sub[15]);
312-
res.w16[b] = vxsat.w16[b] ? (opb.w16[b][15] ? 16'h8000 : 16'h7FFF) : sub[15:0];
312+
res.w16[b] = &vxsat.w16[b] ? (opb.w16[b][15] ? 16'h8000 : 16'h7FFF) : sub[15:0];
313313
end
314314
EW32: for (int b = 0; b < 2; b++) begin
315315
automatic logic [32:0] sub = opb.w32[b] - opa.w32[b];
316316
vxsat.w32[b] = (!opb.w32[b][31] & opa.w32[b][31] & sub[31]) |
317317
(opb.w32[b][31] & !opa.w32[b][31] & !sub[31]);
318-
res.w32[b] = vxsat.w32[b] ? (opb.w32[b][31] ? 32'h80000000 : 32'h7FFFFFFF) : sub[31:0];
318+
res.w32[b] = &vxsat.w32[b] ? (opb.w32[b][31] ? 32'h80000000 : 32'h7FFFFFFF) : sub[31:0];
319319
end
320320
EW64: for (int b = 0; b < 1; b++) begin
321321
automatic logic [64:0] sub = opb.w64[b] - opa.w64[b];
322322
vxsat.w64[b] = (!opb.w64[b][63] & opa.w64[b][63] & sub[63]) |
323323
(opb.w64[b][63] & !opa.w64[b][63] & !sub[63]);
324-
res.w64[b] = vxsat.w64[b] ? (opb.w64[b][63] ? 64'h8000000000000000 : 64'h7FFFFFFFFFFFFFFF) : sub[63:0];
324+
res.w64[b] = &vxsat.w64[b] ? (opb.w64[b][63] ? 64'h8000000000000000 : 64'h7FFFFFFFFFFFFFFF) : sub[63:0];
325325
end
326326
endcase
327327
VASUB, VASUBU: if (FixPtSupport == FixedPointEnable) begin
@@ -335,7 +335,7 @@ module simd_alu import ara_pkg::*; import rvv_pkg::*; #(
335335
2'b10: r = 1'b0;
336336
2'b11: r = !sub[1] & (sub[0]!=0);
337337
endcase
338-
res.w8[b] = (op_i == VASUBU) ? (sub[7:0] >> 1) + r : ($signed(sub[7:0]) >>> 1) + r;
338+
res.w8[b] = (op_i == VASUBU) ? (sub[7:0] >> 1) + {7'b0, r} : $unsigned(($signed(sub[7:0]) >>> 1) + $signed({7'b0, r}));
339339
end
340340
EW16: for (int b = 0; b < 4; b++) begin
341341
automatic logic [ 16:0] sub = opb.w16[b] - opa.w16[b];
@@ -345,7 +345,7 @@ module simd_alu import ara_pkg::*; import rvv_pkg::*; #(
345345
2'b10: r = 1'b0;
346346
2'b11: r = !sub[1] & (sub[0]!=0);
347347
endcase
348-
res.w16[b] = (op_i == VASUBU) ? (sub[15:0] >> 1) + r : ($signed(sub[15:0]) >>> 1) + r;
348+
res.w16[b] = (op_i == VASUBU) ? (sub[15:0] >> 1) + {15'b0, r} : $unsigned(($signed(sub[15:0]) >>> 1) + $signed({15'b0, r}));
349349
end
350350
EW32: for (int b = 0; b < 2; b++) begin
351351
automatic logic [ 32:0] sub = opb.w32[b] - opa.w32[b];
@@ -355,7 +355,7 @@ module simd_alu import ara_pkg::*; import rvv_pkg::*; #(
355355
2'b10: r = 1'b0;
356356
2'b11: r = !sub[1] & (sub[0]!=0);
357357
endcase
358-
res.w32[b] = (op_i == VASUBU) ? (sub[31:0] >> 1) + r : ($signed(sub[31:0]) >>> 1) + r;
358+
res.w32[b] = (op_i == VASUBU) ? (sub[31:0] >> 1) + {31'b0, r} : $unsigned(($signed(sub[31:0]) >>> 1) + $signed({31'b0, r}));
359359
end
360360
EW64: for (int b = 0; b < 1; b++) begin
361361
automatic logic [ 64:0] sub = opb.w64[b] - opa.w64[b];
@@ -365,7 +365,7 @@ module simd_alu import ara_pkg::*; import rvv_pkg::*; #(
365365
2'b10: r = 1'b0;
366366
2'b11: r = !sub[1] & (sub[0]!=0);
367367
endcase
368-
res.w64[b] = (op_i == VASUBU) ? (sub[63:0] >> 1) + r : ($signed(sub[63:0]) >>> 1) + r;
368+
res.w64[b] = (op_i == VASUBU) ? (sub[63:0] >> 1) + {63'b0, r} : $unsigned(($signed(sub[63:0]) >>> 1) + $signed({63'b0, r}));
369369
end
370370
endcase end
371371

@@ -446,19 +446,19 @@ module simd_alu import ara_pkg::*; import rvv_pkg::*; #(
446446
// Fixed point clip instructions
447447
VNCLIP: if (FixPtSupport == FixedPointEnable) unique case (vew_i)
448448
EW8 : for (int b = 0; b < 4; b++) begin
449-
automatic logic [15:0] clip = $signed(opb.w16[b]) >>> opa.w16[b][3:0];
449+
automatic logic [15:0] clip = $unsigned($signed(opb.w16[b]) >>> opa.w16[b][3:0]);
450450
vxsat.w8[b] = |clip[15:8];
451-
res.w8 [2*b + narrowing_select_i] = ($signed(opb.w16[b]) >>> opa.w16[b][3:0]) + rm[b];
451+
res.w8 [2*b + narrowing_select_i] = $unsigned(($signed(opb.w16[b]) >>> opa.w16[b][3:0]) + $signed(rm[b]));
452452
end
453453
EW16: for (int b = 0; b < 2; b++) begin
454-
automatic logic [31:0] clip = $signed(opb.w32[b]) >>> opa.w32[b][4:0];
454+
automatic logic [31:0] clip = $unsigned($signed(opb.w32[b]) >>> opa.w32[b][4:0]);
455455
vxsat.w8[b] = |clip[31:16];
456-
res.w16[2*b + narrowing_select_i] = ($signed(opb.w32[b]) >>> opa.w32[b][4:0]) + rm[b];
456+
res.w16[2*b + narrowing_select_i] = $unsigned(($signed(opb.w32[b]) >>> opa.w32[b][4:0]) + $signed(rm[b]));
457457
end
458458
EW32: for (int b = 0; b < 1; b++) begin
459459
automatic logic [63:0] clip = $signed(opb.w64[b]) >>> opa.w64[b][5:0];
460460
vxsat.w8[b] = |clip[63:32];
461-
res.w32[2*b + narrowing_select_i] = ($signed(opb.w64[b]) >>> opa.w64[b][5:0]) + rm[b];
461+
res.w32[2*b + narrowing_select_i] = $unsigned(($signed(opb.w64[b]) >>> opa.w64[b][5:0]) + $signed(rm[b]));
462462
end
463463
endcase
464464
VNCLIPU: if (FixPtSupport == FixedPointEnable) unique case (vew_i)

‎hardware/src/lane/vmfpu.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -844,7 +844,7 @@ module vmfpu import ara_pkg::*; import rvv_pkg::*; import fpnew_pkg::*;
844844
EnableVectors: 1'b1,
845845
EnableNanBox : 1'b1,
846846
FpFmtMask : {RVVF(FPUSupport), RVVD(FPUSupport), RVVH(FPUSupport), RVVB(FPUSupport), RVVHA(FPUSupport), RVVBA(FPUSupport)},
847-
IntFmtMask : {logic'(RVVB(FPUSupport) || RVVBA(FPUSupport)), 1'b1, 1'b1, 1'b1}
847+
IntFmtMask : {RVVB(FPUSupport) || RVVBA(FPUSupport), 1'b1, 1'b1, 1'b1}
848848
};
849849

850850
// Implementation (number of registers etc)

‎hardware/src/sldu/sldu.sv‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -612,7 +612,7 @@ module sldu import ara_pkg::*; import rvv_pkg::*; #(
612612
// Filled up a word to the VRF or finished the instruction
613613
if (out_pnt_d == NrLanes * 8 || issue_cnt_q <= byte_count) begin
614614
// Reset the pointer
615-
out_pnt_d = vinsn_issue_q.vfu inside {VFU_Alu, VFU_MFpu} ? {'0, red_stride_cnt_d, 3'b0} : '0;
615+
out_pnt_d = vinsn_issue_q.vfu inside {VFU_Alu, VFU_MFpu} ? {{idx_width(NrLanes*(StrbWidth-1)){1'b0}}, red_stride_cnt_d, 3'b0} : '0;
616616
// We used all the bits of the mask
617617
if (vinsn_issue_q.op inside {VSLIDEUP, VSLIDEDOWN})
618618
mask_ready_d = !vinsn_issue_q.vm;
@@ -754,7 +754,7 @@ module sldu import ara_pkg::*; import rvv_pkg::*; #(
754754
// Update the p2 stride
755755
p2_stride_gen_update_d = 1'b1;
756756
// Commit the final result
757-
if (p2_stride_gen_popc_q == {'0, 1'b1} && result_queue_empty) begin
757+
if (p2_stride_gen_popc_q == {{(idx_width(idx_width(8*NrLanes))-1){1'b0}}, 1'b1} && result_queue_empty) begin
758758
state_d = SLIDE_NP2_COMMIT;
759759
// Prepare the write pointer
760760
result_queue_write_pnt_d = NP2_RESULT_PNT;

‎hardware/src/vlsu/addrgen.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -970,7 +970,7 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
970970
// Generate an error
971971
idx_op_error_d = 1'b1;
972972
// Forward next vstart info to the dispatcher
973-
addrgen_exception_vstart_d = (addrgen_req.len - axi_addrgen_q.len) >> axi_addrgen_q.vew - 1;
973+
addrgen_exception_vstart_d = (addrgen_req.len - axi_addrgen_q.len) >> (axi_addrgen_q.vew - 1);
974974
addrgen_req_ready = 1'b1;
975975
axi_addrgen_state_d = AXI_ADDRGEN_IDLE;
976976
end : eew_misaligned_error

‎hardware/src/vlsu/vldu.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -419,7 +419,7 @@ module vldu import ara_pkg::*; import rvv_pkg::*; #(
419419
vrf_word_byte_pnt_d = '0;
420420
vrf_word_byte_cnt_d = '0;
421421
// Account for the results that were issued
422-
if (seq_word_wr_offset_q) begin
422+
if (seq_word_wr_offset_q != '0) begin
423423
vrf_eff_write_bytes = (NrLanes * DataWidthB);
424424
end else begin
425425
// First payload of the vector instruction

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