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Add saturating add/sub intrinsics to RISC-V vector backend #632

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Add saturating add/sub intrinsics to RISC-V vector backend

Add saturating add/sub intrinsics to RISC-V vector backend #632

Re-run triggered July 6, 2026 20:57
@abadamsabadams
#9185
rajeshgangam:riscv-saturating-ops
Status Success
Total duration 1h 6m 26s
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testing-arm-linux.yml

on: pull_request
Matrix: arm-linux
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arm-32 / ci-llvm-main
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arm-32 / ci-llvm-21
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arm-64 / ci-llvm-21
Failed to save: Unable to reserve cache with key setup-uv-2-aarch64-unknown-linux-gnu-ubuntu-24.04-3.12.3-pruned-666d79d5ae9d7e6760a6ff7d0aff64d02ed718b27552c0df6ff70d03b71619b0, another job may be creating this cache.
arm-64 / ci-llvm-22
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arm-64 / ci-llvm-main
Failed to save: Unable to reserve cache with key setup-uv-2-aarch64-unknown-linux-gnu-ubuntu-24.04-3.12.3-pruned-666d79d5ae9d7e6760a6ff7d0aff64d02ed718b27552c0df6ff70d03b71619b0, another job may be creating this cache.