Skip to content

regs_access() for RISC-V yield error #2406

@KelvinChung2000

Description

@KelvinChung2000

Work environment

Questions Answers
OS/arch/bits Pop OS
Architecture x86
Source of Capstone pip
Version/git commit v5.0.1

Expected behavior

regs_access() should return the read and write regs

Actual behavior

Rasing error on unsupported architecture

Steps to reproduce the behavior

from capstone import Cs
from capstone import CS_ARCH_RISCV, CS_MODE_RISCV64

CODE = b"\x83\x3e\x05\x08"
md = Cs(CS_ARCH_RISCV, CS_MODE_RISCV64)
for insn in md.disasm(CODE, 0):
    print(insn.bytes)
    print(f"{insn.mnemonic} {insn.op_str}")
    print(insn.regs_access())

Additional Logs, screenshots, source code, configuration dump, ...

image

Metadata

Metadata

Assignees

No one assigned

    Labels

    RISCVArchbugSomething is not working as it should

    Type

    No type

    Projects

    No projects

    Relationships

    None yet

    Development

    No branches or pull requests

    Issue actions