s390x: implement & test smul_overflow

Author: theotherjimmy

cranelift/codegen/src/isa/s390x/inst.isle

@@ -1099,8 +1099,10 @@
     (SubLogical64)
     (SubLogical64Ext32)
     (Mul32)
+    (Mul32CC)
     (Mul32Ext16)
     (Mul64)
+    (Mul64CC)
     (Mul64Ext16)
     (Mul64Ext32)
     (And32)
@@ -4040,6 +4042,10 @@
 (rule (aluop_mul $I32) (ALUOp.Mul32))
 (rule (aluop_mul $I64) (ALUOp.Mul64))
 
+(decl aluop_mul_cc (Type) ALUOp)
+(rule (aluop_mul_cc $I32) (ALUOp.Mul32CC))
+(rule (aluop_mul_cc $I64) (ALUOp.Mul64CC))
+
 (decl aluop_mul_sext16 (Type) ALUOp)
 (rule (aluop_mul_sext16 $I16) (ALUOp.Mul32Ext16))
 (rule (aluop_mul_sext16 $I32) (ALUOp.Mul32Ext16))
@@ -4051,6 +4057,10 @@
 (decl mul_reg (Type Reg Reg) Reg)
 (rule (mul_reg ty x y) (alu_rrr ty (aluop_mul ty) x y))
 
+(decl mul_reg_with_flags_paired (Type Reg Reg) ProducesFlags)
+(rule (mul_reg_with_flags_paired ty x y)
+     (alu_rrr_with_flags_paired ty (aluop_mul_cc ty) x y))
+
 (decl mul_reg_sext32 (Type Reg Reg) Reg)
 (rule (mul_reg_sext32 ty x y) (alu_rr ty (aluop_mul_sext32 ty) x y))
 

cranelift/codegen/src/isa/s390x/inst/emit.rs

@@ -1516,7 +1516,9 @@ impl Inst {
                     ALUOp::SubLogical32 => (0xb9fb, true), // SLRK
                     ALUOp::SubLogical64 => (0xb9eb, true), // SLGRK
                     ALUOp::Mul32 => (0xb9fd, true),        // MSRKC
+                    ALUOp::Mul32CC => (0xb9fd, false),     // MSRKC
                     ALUOp::Mul64 => (0xb9ed, true),        // MSGRKC
+                    ALUOp::Mul64CC => (0xb9ed, false),     // MSGRKC
                     ALUOp::And32 => (0xb9f4, true),        // NRK
                     ALUOp::And64 => (0xb9e4, true),        // NGRK
                     ALUOp::Orr32 => (0xb9f6, true),        // ORK

cranelift/codegen/src/isa/s390x/inst/mod.rs

@@ -1296,7 +1296,9 @@ impl Inst {
                     ALUOp::SubLogical32 => ("slrk", true),
                     ALUOp::SubLogical64 => ("slgrk", true),
                     ALUOp::Mul32 => ("msrkc", true),
+                    ALUOp::Mul32CC => ("msrkc", false),
                     ALUOp::Mul64 => ("msgrkc", true),
+                    ALUOp::Mul64CC => ("msgrkc", false),
                     ALUOp::And32 => ("nrk", true),
                     ALUOp::And64 => ("ngrk", true),
                     ALUOp::Orr32 => ("ork", true),

cranelift/codegen/src/isa/s390x/lower.isle

@@ -4399,6 +4399,29 @@
               (intcc_as_cond (IntCC.Equal)))))))
         (output_pair result of)))
 
+;;;; Rules for `smul_overflow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+;; For fit-in-16 bit integers, we shift just the rhs into the most
+;; significant positions of its 32-bit register, use the codition
+;; codes for the overflow, and shifting back into the expected
+;; least-significant position to generate the result.
+(rule 1 (lower (smul_overflow (fits_in_16 ty) x y))
+      (let ((y_ext Reg (sext32_reg ty y))
+            (x_shifted Reg (lshl_imm $I32 x (type_shift_up ty)))
+            (producer ProducesFlags
+              (mul_reg_with_flags_paired $I32 x_shifted y_ext))
+            (overflow Reg (lower_bool $I8 (bool
+              (produces_flags_ignore producer)
+              (mask_as_cond 1))))
+            (out Reg (lshr_imm $I32
+              (produces_flags_get_reg producer)
+              (type_shift_up ty))))
+        (output_pair out overflow)))
+
+;; Use flags generated by the add instruction to handle overflow
+(rule 0 (lower (smul_overflow (ty_32_or_64 ty) x y))
+      (overflow_and_result_from_producer (mul_reg_with_flags_paired ty x y) (mask_as_cond 1)))
+
 ;;;; Rules for `return` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 (rule (lower (return args))

cranelift/filetests/filetests/isa/s390x/smul_overflow.clif

@@ -0,0 +1,95 @@
+test compile precise-output
+target s390x
+
+function %f2(i8, i8) -> i8, i8 {
+block0(v0: i8, v1: i8):
+    v2, v3 = smul_overflow v0, v1
+    return v2, v3
+}
+
+; VCode:
+; block0:
+;   lbr %r3, %r3
+;   sllk %r5, %r2, 24
+;   msrkc %r2, %r5, %r3
+;   lhi %r3, 0
+;   lochio %r3, 1
+;   srlk %r2, %r2, 24
+;   br %r14
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   lbr %r3, %r3
+;   sllk %r5, %r2, 0x18
+;   msrkc %r2, %r5, %r3
+;   lhi %r3, 0
+;   lochio %r3, 1
+;   srlk %r2, %r2, 0x18
+;   br %r14
+
+function %f2(i16, i16) -> i16, i8 {
+block0(v0: i16, v1: i16):
+    v2, v3 = smul_overflow v0, v1
+    return v2, v3
+}
+
+; VCode:
+; block0:
+;   lhr %r3, %r3
+;   sllk %r5, %r2, 16
+;   msrkc %r2, %r5, %r3
+;   lhi %r3, 0
+;   lochio %r3, 1
+;   srlk %r2, %r2, 16
+;   br %r14
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   lhr %r3, %r3
+;   sllk %r5, %r2, 0x10
+;   msrkc %r2, %r5, %r3
+;   lhi %r3, 0
+;   lochio %r3, 1
+;   srlk %r2, %r2, 0x10
+;   br %r14
+
+function %f2(i32, i32) -> i32, i8 {
+block0(v0: i32, v1: i32):
+    v2, v3 = smul_overflow v0, v1
+    return v2, v3
+}
+
+; VCode:
+; block0:
+;   msrkc %r2, %r2, %r3
+;   lhi %r3, 0
+;   lochio %r3, 1
+;   br %r14
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   msrkc %r2, %r2, %r3
+;   lhi %r3, 0
+;   lochio %r3, 1
+;   br %r14
+
+function %f4(i64, i64) -> i64, i8 {
+block0(v0: i64, v1: i64):
+    v2, v3 = smul_overflow v0, v1
+    return v2, v3
+}
+
+; VCode:
+; block0:
+;   msgrkc %r2, %r2, %r3
+;   lhi %r3, 0
+;   lochio %r3, 1
+;   br %r14
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   msgrkc %r2, %r2, %r3
+;   lhi %r3, 0
+;   lochio %r3, 1
+;   br %r14
+

cranelift/filetests/filetests/runtests/smul_overflow.clif

@@ -2,6 +2,7 @@ test interpret
 test run
 target x86_64
 target x86_64 has_bmi2
+target s390x
 target aarch64
 
 function %smulof_i64(i64, i64) -> i64, i8 {