s390x: implement & test smul_overflow

Author: theotherjimmy

cranelift/codegen/src/isa/s390x/lower.isle

@@ -4060,6 +4060,18 @@
 (rule 1 (lower (has_type (fits_in_32 ty) (umul_overflow x y)))
       (split_into_result_and_overflow ty (mul_reg $I64 (zext64_reg ty x) (zext64_reg ty y))))
 
+;;;; Rules for `smul_overflow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+;; Use flags generated by the add instruction to handle overflow
+(rule 0 (lower (has_type $I64 (smul_overflow x y)))
+      ;; Note: x y is backwards to avoid emitting 2 spurious lgr instructions
+      ;; See the diff above in the umul_overflow section
+      (let ((intermediate RegPair (smul_wide y x)))
+        (output_pair (regpair_hi intermediate) (regpair_lo intermediate))))
+
+(rule 1 (lower (has_type (fits_in_32 ty) (smul_overflow x y)))
+      (split_into_result_and_overflow ty (mul_reg $I64 (sext64_reg ty y) (sext64_reg ty x))))
+
 ;;;; Rules for `return` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 (rule (lower (return args))

cranelift/filetests/filetests/isa/s390x/smul_overflow.clif

@@ -0,0 +1,85 @@
+test compile precise-output
+target s390x
+
+function %f2(i8, i8) -> i8, i8 {
+block0(v0: i8, v1: i8):
+    v2, v3 = smul_overflow v0, v1
+    return v2, v3
+}
+
+; VCode:
+; block0:
+;   lgbr %r5, %r3
+;   lgbr %r3, %r2
+;   msgrkc %r2, %r5, %r3
+;   srlk %r3, %r2, 8
+;   br %r14
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   lgbr %r5, %r3
+;   lgbr %r3, %r2
+;   msgrkc %r2, %r5, %r3
+;   srlk %r3, %r2, 8
+;   br %r14
+
+function %f2(i16, i16) -> i16, i8 {
+block0(v0: i16, v1: i16):
+    v2, v3 = smul_overflow v0, v1
+    return v2, v3
+}
+
+; VCode:
+; block0:
+;   lghr %r5, %r3
+;   lghr %r3, %r2
+;   msgrkc %r2, %r5, %r3
+;   srlk %r3, %r2, 16
+;   br %r14
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   lghr %r5, %r3
+;   lghr %r3, %r2
+;   msgrkc %r2, %r5, %r3
+;   srlk %r3, %r2, 0x10
+;   br %r14
+
+function %f2(i32, i32) -> i32, i8 {
+block0(v0: i32, v1: i32):
+    v2, v3 = smul_overflow v0, v1
+    return v2, v3
+}
+
+; VCode:
+; block0:
+;   lgfr %r5, %r3
+;   lgfr %r3, %r2
+;   msgrkc %r2, %r5, %r3
+;   srlg %r3, %r2, 32
+;   br %r14
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   lgfr %r5, %r3
+;   lgfr %r3, %r2
+;   msgrkc %r2, %r5, %r3
+;   srlg %r3, %r2, 0x20
+;   br %r14
+
+function %f4(i64, i64) -> i64, i8 {
+block0(v0: i64, v1: i64):
+    v2, v3 = smul_overflow v0, v1
+    return v2, v3
+}
+
+; VCode:
+; block0:
+;   mgrk %r2, %r3, %r2
+;   br %r14
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   mgrk %r2, %r3, %r2
+;   br %r14
+