See Vitis AI Development Environment on amd.com |
The AIE-ML Development Feature Tutorials highlight specific features and flows to help you develop AIE-ML applications.
| Tutorial | Description |
| A to Z Bare-metal Flow | In this tutorial you create a custom bare-metal platform and integrate a bare-metal host application with an AI Engine graph and PL kernels. |
| Using GMIO with AIE-ML | In this tutorial, you use global memory input/output (GMIO) to share data between the AIE‑ML and external double data rate (DDR) memory. |
| Runtime Parameter Reconfiguration | In this tutorial, you learn how to dynamically update AIE-ML runtime parameters. |
| Packet Switching | In this tutorial, you implement data packet switching in AIE‑ML designs to optimize processing efficiency. |
| AI Engine Versal Integration for Hardware Emulation and Hardware | In this tutorial, you create a system design that runs on the AIE-ML, processing system (PS), and programmable logic (PL), then validate it using hardware emulation. |
| AI Engine-ML Performance Analysis Tutorial | In this tutorial, you learn performance analysis and optimization methods, and explore how synchronization works during graph execution. You also analyze a hang issue using an example. |
| AIE Compiler Features | In this tutorial, you learn features that improve AIE and AIE-ML programming, creating more readable and efficient code than earlier compiler versions. |
| Matrix Compute with Vitis Libraries | In this tutorial, you use matrix multiplication/general matrix multiply (GEMM) from the DSP Vitis library. You examine design requirements and configure parameters accordingly. Finally, you migrate the design to the AIE‑ML architecture and compare its performance with the AIE architecture. |
| Tiling Parameter Programming | In this tutorial you learn how to use a major feature of AIE-ML devices: tiling parameters. These parameters apply to all memory levels of the AIE-ML. You use them in local memory (memory modules) with kernel I/O buffers, memory tiles (shared memory in the adaptive data flow (ADF) language) for large intermediate storage, and external double data rate (DDR) memory. |
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