edgeconv_top_synth.v

/* Generated by Yosys 0.9 (git sha1 1979e0b) */

module edgeconv(clk, rst_n, valid_in, pixel_in, digit_out, valid_out);
  wire [3:0] _000_;
  wire [9:0] _001_;
  wire [7:0] _002_;
  wire [31:0] _003_;
  wire [31:0] _004_;
  wire _005_;
  wire _006_;
  wire _007_;
  wire _008_;
  wire _009_;
  wire [3:0] _010_;
  wire _011_;
  wire _012_;
  wire _013_;
  wire _014_;
  wire _015_;
  wire [4:0] _016_;
  wire [1:0] _017_;
  wire _018_;
  wire [1:0] _019_;
  wire _020_;
  wire [9:0] _021_;
  wire [3:0] _022_;
  wire [1:0] _023_;
  wire [1:0] _024_;
  wire _025_;
  wire _026_;
  wire _027_;
  wire [7:0] _028_;
  wire [7:0] _029_;
  wire [19:0] _030_;
  wire [9:0] _031_;
  wire [9:0] _032_;
  wire [31:0] _033_;
  wire [31:0] _034_;
  wire _035_;
  wire _036_;
  wire _037_;
  wire _038_;
  wire _039_;
  wire _040_;
  reg [3:0] class_cnt;
  input clk;
  output [3:0] digit_out;
  wire [15:0] fc_acc;
  wire [3:0] feat_x;
  wire [3:0] feat_y;
  wire [31:0] i;
  wire [31:0] j;
  reg [9:0] pixel_cnt;
  input [7:0] pixel_in;
  wire [7:0] result_reg;
  input rst_n;
  reg [3:0] state;
  input valid_in;
  output valid_out;
  reg valid_reg;
  assign _016_[0] = _003_[0] | _021_[1];
  assign _016_[1] = _021_[2] | _021_[3];
  assign _016_[2] = pixel_cnt[4] | pixel_cnt[5];
  assign _016_[3] = pixel_cnt[6] | pixel_cnt[7];
  assign _016_[4] = _021_[8] | _021_[9];
  assign _017_[0] = _016_[0] | _016_[1];
  assign _017_[1] = _016_[2] | _016_[3];
  assign _018_ = _017_[0] | _017_[1];
  assign _025_ = _018_ | _016_[4];
  assign _019_[0] = _004_[0] | class_cnt[1];
  assign _019_[1] = class_cnt[2] | _022_[3];
  assign _013_ = _019_[0] | _019_[1];
  assign _026_ = _023_[0] | _023_[1];
  assign _010_[1] = state[2] | _007_;
  assign _027_ = _023_[0] | _024_[1];
  assign _020_ = state[3] | _006_;
  assign _010_[0] = _020_ | _005_;
  assign _036_ = state[3] | state[0];
  assign _035_ = state[3] | state[1];
  assign _024_[1] = ~_025_;
  assign _015_ = ~_013_;
  assign _014_ = ~_026_;
  assign _012_ = ~_027_;
  assign _028_[0] = _013_ ? result_reg[0] : pixel_in[0];
  assign _028_[1] = _013_ ? result_reg[1] : pixel_in[1];
  assign _028_[2] = _013_ ? result_reg[2] : pixel_in[2];
  assign _028_[3] = _013_ ? result_reg[3] : pixel_in[3];
  assign _002_[0] = state[1] ? _028_[0] : result_reg[0];
  assign _002_[1] = state[1] ? _028_[1] : result_reg[1];
  assign _002_[2] = state[1] ? _028_[2] : result_reg[2];
  assign _002_[3] = state[1] ? _028_[3] : result_reg[3];
  assign _031_[0] = _025_ ? _003_[0] : 1'h0;
  assign _031_[1] = _025_ ? _003_[1] : 1'h0;
  assign _031_[2] = _025_ ? _003_[2] : 1'h0;
  assign _031_[3] = _025_ ? _003_[3] : 1'h0;
  assign _031_[4] = _025_ ? _003_[4] : 1'h0;
  assign _031_[5] = _025_ ? _003_[5] : 1'h0;
  assign _031_[6] = _025_ ? _003_[6] : 1'h0;
  assign _031_[7] = _025_ ? _003_[7] : 1'h0;
  assign _031_[8] = _025_ ? _003_[8] : 1'h0;
  assign _031_[9] = _025_ ? _003_[9] : 1'h0;
  assign _032_[0] = valid_in ? _031_[0] : pixel_cnt[0];
  assign _032_[1] = valid_in ? _031_[1] : pixel_cnt[1];
  assign _032_[2] = valid_in ? _031_[2] : pixel_cnt[2];
  assign _032_[3] = valid_in ? _031_[3] : pixel_cnt[3];
  assign _032_[4] = valid_in ? _031_[4] : pixel_cnt[4];
  assign _032_[5] = valid_in ? _031_[5] : pixel_cnt[5];
  assign _032_[6] = valid_in ? _031_[6] : pixel_cnt[6];
  assign _032_[7] = valid_in ? _031_[7] : pixel_cnt[7];
  assign _032_[8] = valid_in ? _031_[8] : pixel_cnt[8];
  assign _032_[9] = valid_in ? _031_[9] : pixel_cnt[9];
  assign _001_[0] = _036_ ? _030_[10] : pixel_cnt[0];
  assign _001_[1] = _036_ ? _030_[11] : pixel_cnt[1];
  assign _001_[2] = _036_ ? _030_[12] : pixel_cnt[2];
  assign _001_[3] = _036_ ? _030_[13] : pixel_cnt[3];
  assign _001_[4] = _036_ ? _030_[14] : pixel_cnt[4];
  assign _001_[5] = _036_ ? _030_[15] : pixel_cnt[5];
  assign _001_[6] = _036_ ? _030_[16] : pixel_cnt[6];
  assign _001_[7] = _036_ ? _030_[17] : pixel_cnt[7];
  assign _001_[8] = _036_ ? _030_[18] : pixel_cnt[8];
  assign _001_[9] = _036_ ? _030_[19] : pixel_cnt[9];
  assign _000_[0] = _035_ ? _029_[4] : class_cnt[0];
  assign _000_[1] = _035_ ? _029_[5] : class_cnt[1];
  assign _000_[2] = _035_ ? _029_[6] : class_cnt[2];
  assign _000_[3] = _035_ ? _029_[7] : class_cnt[3];
  assign _011_ = ~valid_in;
  reg \result_reg_reg[0] ;
  always @(posedge clk)
      \result_reg_reg[0]  <= _002_[0];
  assign result_reg[0] = \result_reg_reg[0] ;
  reg \result_reg_reg[1] ;
  always @(posedge clk)
      \result_reg_reg[1]  <= _002_[1];
  assign result_reg[1] = \result_reg_reg[1] ;
  reg \result_reg_reg[2] ;
  always @(posedge clk)
      \result_reg_reg[2]  <= _002_[2];
  assign result_reg[2] = \result_reg_reg[2] ;
  reg \result_reg_reg[3] ;
  always @(posedge clk)
      \result_reg_reg[3]  <= _002_[3];
  assign result_reg[3] = \result_reg_reg[3] ;
  always @(posedge clk or negedge rst_n)
    if (!rst_n)
      state[0] <= 1;
    else
      state[0] <= _010_[0];
  always @(posedge clk or negedge rst_n)
    if (!rst_n)
      state[1] <= 0;
    else
      state[1] <= _010_[1];
  always @(posedge clk or negedge rst_n)
    if (!rst_n)
      state[2] <= 0;
    else
      state[2] <= _008_;
  always @(posedge clk or negedge rst_n)
    if (!rst_n)
      state[3] <= 0;
    else
      state[3] <= _009_;
  always @(posedge clk or negedge rst_n)
    if (!rst_n)
      pixel_cnt[0] <= 0;
    else
      pixel_cnt[0] <= _001_[0];
  always @(posedge clk or negedge rst_n)
    if (!rst_n)
      pixel_cnt[1] <= 0;
    else
      pixel_cnt[1] <= _001_[1];
  always @(posedge clk or negedge rst_n)
    if (!rst_n)
      pixel_cnt[2] <= 0;
    else
      pixel_cnt[2] <= _001_[2];
  always @(posedge clk or negedge rst_n)
    if (!rst_n)
      pixel_cnt[3] <= 0;
    else
      pixel_cnt[3] <= _001_[3];
  always @(posedge clk or negedge rst_n)
    if (!rst_n)
      pixel_cnt[4] <= 0;
    else
      pixel_cnt[4] <= _001_[4];
  always @(posedge clk or negedge rst_n)
    if (!rst_n)
      pixel_cnt[5] <= 0;
    else
      pixel_cnt[5] <= _001_[5];
  always @(posedge clk or negedge rst_n)
    if (!rst_n)
      pixel_cnt[6] <= 0;
    else
      pixel_cnt[6] <= _001_[6];
  always @(posedge clk or negedge rst_n)
    if (!rst_n)
      pixel_cnt[7] <= 0;
    else
      pixel_cnt[7] <= _001_[7];
  always @(posedge clk or negedge rst_n)
    if (!rst_n)
      pixel_cnt[8] <= 0;
    else
      pixel_cnt[8] <= _001_[8];
  always @(posedge clk or negedge rst_n)
    if (!rst_n)
      pixel_cnt[9] <= 0;
    else
      pixel_cnt[9] <= _001_[9];
  always @(posedge clk or negedge rst_n)
    if (!rst_n)
      class_cnt[0] <= 0;
    else
      class_cnt[0] <= _000_[0];
  always @(posedge clk or negedge rst_n)
    if (!rst_n)
      class_cnt[1] <= 0;
    else
      class_cnt[1] <= _000_[1];
  always @(posedge clk or negedge rst_n)
    if (!rst_n)
      class_cnt[2] <= 0;
    else
      class_cnt[2] <= _000_[2];
  always @(posedge clk or negedge rst_n)
    if (!rst_n)
      class_cnt[3] <= 0;
    else
      class_cnt[3] <= _000_[3];
  always @(posedge clk or negedge rst_n)
    if (!rst_n)
      valid_reg <= 0;
    else
      valid_reg <= state[3];
  assign _021_[1] = pixel_cnt[1] ^ 1'h1;
  assign _021_[2] = pixel_cnt[2] ^ 1'h1;
  assign _021_[3] = pixel_cnt[3] ^ 1'h1;
  assign _021_[8] = pixel_cnt[8] ^ 1'h1;
  assign _021_[9] = pixel_cnt[9] ^ 1'h1;
  assign _004_[0] = class_cnt[0] ^ 1'h1;
  assign _022_[3] = class_cnt[3] ^ 1'h1;
  assign _009_ = _015_ & state[1];
  assign _008_ = _014_ & state[0];
  assign _023_[1] = _024_[1] ^ 1'h1;
  assign _005_ = _011_ & state[0];
  assign _023_[0] = valid_in ^ 1'h1;
  assign _007_ = _013_ & state[1];
  assign _006_ = _012_ & state[0];
  assign _030_[10] = _032_[0] & state[0];
  assign _030_[11] = _032_[1] & state[0];
  assign _030_[12] = _032_[2] & state[0];
  assign _030_[13] = _032_[3] & state[0];
  assign _030_[14] = _032_[4] & state[0];
  assign _030_[15] = _032_[5] & state[0];
  assign _030_[16] = _032_[6] & state[0];
  assign _030_[17] = _032_[7] & state[0];
  assign _030_[18] = _032_[8] & state[0];
  assign _030_[19] = _032_[9] & state[0];
  assign _029_[4] = _004_[0] & state[1];
  assign _029_[5] = _004_[1] & state[1];
  assign _029_[6] = _004_[2] & state[1];
  assign _029_[7] = _004_[3] & state[1];
  assign _003_[0] = pixel_cnt[0] ^ 1'h1;
  assign _003_[1] = pixel_cnt[1] ^ pixel_cnt[0];
  assign _003_[2] = pixel_cnt[2] ^ _033_[1];
  assign _003_[3] = pixel_cnt[3] ^ _033_[2];
  assign _003_[4] = pixel_cnt[4] ^ _033_[3];
  assign _003_[5] = pixel_cnt[5] ^ _033_[4];
  assign _003_[6] = pixel_cnt[6] ^ _033_[5];
  assign _003_[7] = pixel_cnt[7] ^ _033_[6];
  assign _003_[8] = pixel_cnt[8] ^ _033_[7];
  assign _003_[9] = pixel_cnt[9] ^ _033_[8];
  assign _004_[1] = class_cnt[1] ^ class_cnt[0];
  assign _004_[2] = class_cnt[2] ^ _034_[1];
  assign _004_[3] = class_cnt[3] ^ _034_[2];
  assign _034_[2] = class_cnt[2] & _034_[1];
  assign _034_[1] = class_cnt[1] & class_cnt[0];
  assign _033_[8] = pixel_cnt[8] & _033_[7];
  assign _033_[6] = pixel_cnt[6] & _033_[5];
  assign _033_[4] = pixel_cnt[4] & _033_[3];
  assign _033_[2] = pixel_cnt[2] & _033_[1];
  assign _033_[5] = _038_ & _033_[3];
  assign _040_ = _039_ & _038_;
  assign _039_ = pixel_cnt[7] & pixel_cnt[6];
  assign _038_ = pixel_cnt[5] & pixel_cnt[4];
  assign _037_ = pixel_cnt[3] & pixel_cnt[2];
  assign _033_[7] = _040_ & _033_[3];
  assign _033_[3] = _037_ & _033_[1];
  assign _033_[1] = pixel_cnt[1] & pixel_cnt[0];
  assign _003_[31:11] = 21'h000000;
  assign _004_[31:5] = 27'h0000000;
  assign _010_[3:2] = { _009_, _008_ };
  assign { _021_[7:4], _021_[0] } = { pixel_cnt[7:4], _003_[0] };
  assign _022_[2:0] = { class_cnt[2:1], _004_[0] };
  assign _024_[0] = _023_[0];
  assign _029_[3:0] = 4'h0;
  assign _030_[9:0] = 10'h000;
  assign { _033_[31:9], _033_[0] } = { 22'h000000, _003_[10], pixel_cnt[0] };
  assign { _034_[31:3], _034_[0] } = { 28'h0000000, _004_[4], class_cnt[0] };
  assign digit_out = result_reg[3:0];
  assign fc_acc = 16'h0000;
  assign feat_x = 4'h0;
  assign feat_y = 4'h0;
  assign i = 32'd10;
  assign j = 32'd196;
  assign valid_out = valid_reg;
endmodule

module edgeconv_top(clk, rst_n, valid_in, pixel_in, digit_out, valid_out);
  input clk;
  output [3:0] digit_out;
  input [7:0] pixel_in;
  input rst_n;
  input valid_in;
  output valid_out;
  edgeconv core (
    .clk(clk),
    .digit_out(digit_out),
    .pixel_in(pixel_in),
    .rst_n(rst_n),
    .valid_in(valid_in),
    .valid_out(valid_out)
  );
endmodule